Final Testbench

Gün 7: Bitirme Projesi - Bölüm 2 | Tüm bileşenleri bir araya getiren son testbench

Kaynak Kod

// =============================================================================
// GUN 7 KONU 6: Final Testbench Top-Level
// =============================================================================
// =============================================================================

`include "6_2_transaction.sv"
`include "7_5_coverage.sv"
`include "6_3_generator.sv"
`include "6_4_driver.sv"
`include "7_1_monitor.sv"
`include "7_2_scoreboard.sv"
`include "7_3_environment.sv"
`include "7_4_test.sv"
`include "alu_if.sv"

module tb_top_final;

  // Clock generation
  logic clk = 0;
  always #5 clk = ~clk;  // 100MHz (period = 10ns)

  // Interface
  alu_if aif(clk);

  // DUT (Design Under Test)
  alu dut (
    .clk       (aif.clk),
    .rst_n     (aif.rst_n),
    .in_valid  (aif.in_valid),
    .operand_a (aif.operand_a),
    .operand_b (aif.operand_b),
    .opcode    (aif.opcode),
    .out_valid (aif.out_valid),
    .result    (aif.result),
    .flags     (aif.flags)
  );

  // Test selection
  initial begin
    ALU_Base_Test test;
    
    // Declare handles for derived classes
    ALU_Random_Test rand_test;
    ALU_Corner_Test corner_test;
    
    string test_name;

    // Test selection from command line: +TEST=Random_Test
    if (!$value$plusargs("TEST=%s", test_name))
      test_name = "Random_Test";  // Default

    $display("============================================================");
    $display("  ALU VERIFICATION PROJECT - FINAL");
    $display("  Selected Test: %s", test_name);
    $display("============================================================");

    case (test_name)
      "Random_Test": begin
        rand_test = new(aif, aif);
        test = rand_test;
      end
      "Corner_Test": begin
        corner_test = new(aif, aif);
        test = corner_test;
      end
      default: begin
        $display("  Unknown test: %s, Random_Test is being used", test_name);
        rand_test = new(aif, aif);
        test = rand_test;
      end
    endcase

    test.run();

    $display("\n============================================================");
    $display("  SIMULATION COMPLETED");
    $display("============================================================");
    $finish;
  end

  // VCD waveform
  initial begin
    $dumpfile("alu_tb_final.vcd");
    $dumpvars(0, tb_top_final);
  end

endmodule